Low Power Issues In VLSI Testing

Testing VLSI circuits bridges the gap between the imperfection of integrated circuit manufacturing and consumer expectations of flawless products (production testing) as well as the desire of the user for continues correct product operation (on-the-field testing). This lecture covers the problem of VLSI circuit testing, the design of circuits for testability and the design of built-in self-testing circuits. Emphasis is given on the low power aspects of VLSI testing and specifically on techniques for minimizing power and energy dissipation during testing.

The lecture’s material is:

  • Introduction to VLSI testing
  • Power dissipation during testing
  • Power consumption minimization during external testing of combinational circuits
  • Low-power scan-based external testing
  • Low-power test-per-clock BIST
  • Low-power test-per-scan BIST
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