Logic Synthesis of Asynchronous Control Circuits from Causality Relations
This talk is concerned with asynchronous digital circuits and to a systematic logic synthesis design flow for their implementation. It presents the underlying theory and logic synthesis flow for implementing asynchronous circuits from Causality Relations, from the specification of the circuit as a causality graph, i.e. a graph, the edges of which represent dependencies between signal transitions in the circuit’s specification. Next, a logic synthesis flow is described for transforming the causality graph into binary equations and ultimately map the circuit to gates of a given technology library. The implementability conditions for a graph to possess a circuit representation are detailed along with the trade-off between adding timing assumptions and implementing a simpler circuit.